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Novas Makes Transaction-Based Analysis More Accessible To HDL Users; Powerful New Engine Leverages SystemVerilog to Simplify Understanding of Complex Protocols in HDL Designs
SAN JOSE, Calif.—(BUSINESS WIRE)—July 10, 2006—
Novas Software, Inc., the leader in debug systems for
complex chip designs, today introduced a new set of capabilities that
enables designers to easily visualize and debug their complex
communication protocols using transactions. The new capabilities
leverage the SystemVerilog language by allowing users to describe
their protocols using assertion constructs and extract the related
activity as transactions. These capabilities make transaction-based
analysis accessible to all designers, including those designing at the
register transfer level (RTL). The features are available in the new
optional nTX(TM) module for the Novas Verdi(TM) Automated Debug
System.
Transactions Ease Design Understanding
Transactions allow designers to track and visualize the
communication between system components in terms of high-level
operations rather than discrete signal value changes.
Transaction-level abstractions ease understanding of on-chip
communication and bus activity, particularly when a design uses
complex or proprietary protocols. However, due to the lack of a broad
standard that defines how transactions should be described and
evaluated, their use has mainly been limited to engineers willing to
use proprietary languages or designers working in the electronic
system level (ESL) space, where languages such as SystemC have
built-in transaction-related constructs. The new Novas nTX module
overcomes this challenge with an automated methodology for translating
simulator-produced data to transaction-level data for debug and
analysis of HDL designs.
"Transactions hide complicated, low-level details, allowing
analysis to take place at higher levels of abstraction and greatly
simplifying the process of understanding complex system behavior.
However, the benefits of a transaction-based approach have been
enjoyed by a relatively small segment of the design community," said
George Bakewell, director of product marketing at Novas. "With the new
features available in the Verdi nTX module, we've lowered the barrier
to entry for using transactions, making them accessible to anybody
designing with standard HDLs and verifying those designs using popular
verification tools."
Enhanced Transaction-based Debug
At the heart of the Verdi enhanced transaction environment is an
evaluation engine that extracts transactions from signal-level data
based on user-coded SystemVerilog Assertion (SVA) descriptions. SVA
was chosen as the preferred transaction description language for
several reasons: it is part of the increasingly-popular SystemVerilog
standard; its syntax and semantics support temporal aspects critical
to the description of transactions; and its support for local
variables maps nicely into the notion of transaction attributes, which
allow detailed information to be linked with the abstract
transactions.
This flexible, SVA-based evaluation engine makes it possible for
engineers to describe complex, proprietary protocols in a standard
language, automatically extract the related transactions from the
low-level signal details, and view and analyze the operation of their
design more efficiently at the transaction level. In some cases, SVA
code written for use as assertions can be easily re-purposed to drive
the transaction evaluation engine.
This general SVA-based capability complements a ready-made
library, available in object code form, which supports the extraction
of standard protocols - such as AHB, PCI Express, OCP-IP, UART
(RS232), and MPEG2 - from a signal-level database. Together, these
features provide a general way for users to describe and capture
transaction information, whether they're using standard buses with
well-defined protocols or proprietary protocols in the system under
test.
After the transaction extraction process is complete, the
resulting transaction database can be imported into the Verdi
environment for use with powerful transaction-level debug and analysis
capabilities. These include a waveform display that supports
visualization of overlapping transactions and transaction
relationships; a flexible spreadsheet for sorting, filtering, and
isolating the transactions of interest; graphical pie charts and bar
charts for performance analysis; and a unique transaction comparison
engine for high-level analysis across multiple simulations.
Availability
Novas' enhanced transaction capabilities will be available with
the third quarter 2006 release of the Verdi debug system. The Verdi
system is U.S. list priced starting at $12K with new add-on nTX module
available at $6K. For more information on Novas' automated debug
products, visit http://www.novas.com/Solutions/Verdi/.
About Novas
Novas Software, Inc. is the leading provider of design
comprehension solutions for engineers designing complex ICs, embedded
systems and SoCs. Novas' Verdi automated debug and Siloti visibility
enhancement products dramatically accelerate the process for
understanding and correcting design problems starting from
system-level specification through silicon implementation. Novas is
headquartered in San Jose, Calif. with offices in Europe, Japan and
Asia-Pacific. For more information, visit http://www.novas.com or
email info@novas.com.
Verdi and Siloti are trademarks of Novas Software, Inc. All other
trademarks or registered trademarks are the property of their
respective owners.
Note to editors: High-resolution graphics available.
Contact:
Novas Software, Inc., San Jose
Rob van Blommestein, 408-467-7872
Email Contact
or
Public Relations for Novas
Wired Island, Ltd.
Laurie Stanley, 925-224-8762
Email Contact
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